As one of data transmission schemes used in the related art for data transmission between a data input side and a variety of semiconductor devices, there exists a parallel interface that transmits data signals in parallel, i.e., transmits a plurality of bits simultaneously.
For example, in an IC for image processing or an IC for an LCD driver, image data signals and a parallel clock signal (hereinafter, referred to as a clock signal) are inputted from transmission lines on the side of twenty-five input/output (IO) units and then latched in a logic circuit (e.g., a logic unit configured with a level shifter) in the IC.
In order to improve synchronization accuracy of such data signals, etc., it is necessary to match the delays of the data signals and the clock signal from the IO unit to the logic unit.
There have been proposed techniques for matching such delays by making the lengths of wirings that form the transmission lines from the IO unit to the logic unit all equal so that the electrical resistances of the wirings are all equal.
In order to suppress the data signals inputted from the IO unit from chattering, a Schmitt buffer may be disposed, which is one type of hysteresis buffers.
Since the output impedance of the Schmitt buffer is typically high, it tends to depend more on wiring capacitance than on wiring resistance. Accordingly, there has been a problem of relatively long transmission lines in that differences in wiring capacitance are generated between the transmission lines.
Due to such differences in wiring capacitance, it is difficult to match the delay times of data signals and a clock signal in transmission lines, which results in lowering the accuracy of AC timing such as set up time and hold time.